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1 ?2016 integrated device technology, inc. revision d september 27, 2016 general description the 83905 is a low skew, 1-to-6 lvcmos / lvttl fanout buffer. the low impedance lvcmos/lvttl outputs are designed to drive 50 ? series or parallel terminated transmission lines. the effective fanout can be increas ed from 6 to 12 by utilizing the ability of the outputs to drive two series terminated lines. the 83905 is characterized at full 3.3v, 2.5v, and 1.8v, mixed 3.3v/2.5v, 3.3v/1.8v and 2.5v/1.8v output operating supply mode. guaranteed output and part-to-part skew characteristics along with the 1.8v output capab ilities makes the 83905 ideal for high performance, single ended applic ations that also require a limited output voltage. pin assignments features ? six lvcmos / lvttl outputs ? outputs able to drive 12 series terminated lines ? crystal oscillator interface ? crystal input frequency range: 10mhz to 40mhz ? output skew: 80ps (maximum) ? rms phase jitter @ 25mhz, (100hz ? 1mhz): 0.26ps (typical), v dd = v ddo = 2.5v offset noise power 100hz............... ..-129.7 dbc/hz 1khz ............... ....-144.4 dbc/hz 10khz ....... ..........-147.3 dbc/hz 100khz ...............-157.3 dbc/hz ? 5v tolerant enable inputs ? synchronous output enables ? operating power supply modes: full 3.3v, 2.5v, 1.8v mixed 3.3v core/2.5v output operating supply mixed 3.3v core/1.8v output operating supply mixed 2.5v core/1.8v output operating supply ? 0c to 70c ambient operating temperature ? lead-free (rohs 6) packaging block diagram 6 7 8 9 10 19 20 18 17 16 1 2 3 4 5 13 14 15 12 11 gnd v ddo gnd b clk0 b clk1 bclk 4 bclk 5 v ddo gnd gnd v dd b clk2 gnd gnd b clk3 enable1 enable2 xtal_in xtal_ou t nc 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 xtal_in enable 1 bclk5 v ddo bclk4 gnd bclk3 v dd bclk2 gnd bclk1 v ddo bclk0 gnd enable2 x tal_out 83905 16-lead soic, 150 mil 3.9mm x 9.9mm x 1.38mm package body m package top view 16-lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view 83905 20-lead vfqfn 4mm x 4mm x 0.925mm package body k package top view synchronize synchronize bclk 0 bclk 1 bclk 2 bclk 3 bclk 4 bclk 5 xtal_in x tal_out enable 1 enable 2 83905 datasheet low skew, 1:6 crystal-to-lvcmos/ lvttl fanout buffer
2 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet pin descriptions and characteristics table 1. pin descriptions table 2. pin characteristics function table table 3. clock enable function table figure 1. enable timing diagram name type description xtal_out output crystal oscillator in terface. xtal_out is the output. xtal_in input crystal oscillator in terface. xtal_in is the input. enable1, enable2 input clock enable. lvcmos/lvttl interface levels. see table 3. bclk0, bclk1, bclk2, bclk3, bclk4, bclk5 output clock outputs. lvcmos/lvttl interface levels. gnd power power supply ground. v dd power power supply pin. v ddo power output supply pin. nc unused no connect. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf c pd power dissipation capacitance (per output) v ddo = 3.465v 19 pf v ddo = 2.625v 18 pf v ddo = 2.0v 16 pf r out output impedance v ddo = 3.3v 5% 7 ? v ddo = 2.5v 5% 7 ? v ddo = 1.8v 0.2v 10 ? control inputs outputs enable 1 enable2 bclk[0:4] bclk5 0 0 low low 0 1 low toggling 1 0 toggling low 1 1 toggling toggling bclk5 bclk[0:4] enable2 enable1
3 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any condi tions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c table 4b. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c table 4c. power supply dc characteristics, v dd = v ddo = 1.8v 0.2v, t a = 0c to 70c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ? ja 16-lead soic package 16-lead tssop package 20-lead vfqfn package 78.8 ? c/w (0 mps) 100.3 ? c/w (0 mps) 57.5 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 3.135 3.3 3.465 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 5 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable [1:2] = 00 8 ma i ddo output supply current enable [1:2] = 00 4 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 1.6 1.8 2.0 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 5 ma i ddo output supply current enable [1:2] = 00 3 ma
4 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet table 4d. power supply dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = 0c to 70c table 4e. power supply dc characteristics, 3.3v 5%, v ddo = 1.8v 0.2v, t a = 0c to 70c table 4f. power supply dc characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.2v, t a = 0c to 70c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 2.375 2.5 2.625 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 4 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 3.135 3.3 3.465 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 10 ma i ddo output supply current enable [1:2] = 00 3 ma symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5 2.625 v v ddo output supply voltage 1.6 1.8 2.0 v i dd power supply current enable [1:2] = 00 8 ma i ddo output supply current enable [1:2] = 00 3 ma
5 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet table 4g. lvcmos/lvttl dc characteristics, t a = 0c to 70c note 1: outputs terminated with 50 ? to v ddo /2. see parameter measurement information, output load test circuit diagrams. table 5. crystal characteristics symbol parameter test conditio ns minimum typical maximum units v ih input high voltage enable1, enable2 v dd = 3.3v 5% 2 v dd + 0.3 v v dd = 2.5v 5% 1.7 v dd + 0.3 v v dd = 1.8v 0.2v 0.65 * v dd v dd + 0.3 v v il input low voltage enable1, enable2 v dd = 3.3v 5% -0.3 0.8 v v dd = 2.5v 5% -0.3 0.7 v v dd = 1.8v 0.2v -0.3 0.35 * v dd v v oh output high voltage v ddo = 3.3v 5%; note 1 2.6 v v ddo = 2.5v 5%; i oh = -1ma 2.0 v v ddo = 2.5v 5%; note 1 1.8 v v ddo = 1.8v 0.2v; note 1 v ddo - 0.3 v v ol output low voltage; note 1 v ddo = 3.3v 5%; note 1 0.5 v v ddo = 2.5v 5%; i ol = 1ma 0.4 v v ddo = 2.5v 5%; note 1 0.45 v v ddo = 1.8v 0.2v; note 1 0.35 v parameter test cond itions minimum typ ical maximum units mode of oscillation fundamental frequency 10 40 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf drive level 1mw
6 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet ac electrical characteristics table 6a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: see phase noise plot. note 5: these parameters are guaranteed by characterization. not tested in production. table 6b. ac characteristics, v dd = v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: see phase noise plot. note 5: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit(?) rms phase jitter (random); note 4 25mhz, integration range: 100hz ? 1mhz 0.13 ps t r / t f output rise/fall time 20% to 80% 200 800 ps odc output duty cycle 48 52 % t en output enable time; note 5 enable1 4 cycles enable2 4 cycles t dis output disable time; note 5 enable1 4 cycles enable2 4 cycles symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random); note 4 25mhz, integration range: 100hz ? 1mhz 0.26 ps t r / t f output rise/fall time 20% to 80% 200 800 ps odc output duty cycle 47 53 % t en output enable time; note 5 enable1 4 cycles enable2 4 cycles t dis output disable time; note 5 enable1 4 cycles enable2 4 cycles
7 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet table 6c. ac characteristics, v dd = v ddo = 1.8v 0.2v, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. table 6d. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typi cal maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit(?) rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.27 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 47 53 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.14 ps t r / t f output rise/fall time 20% to 80% 200 800 ps odc output duty cycle 48 52 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
8 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet table 6e. ac characteristics, v dd = 3.3v 5%, v ddo = 1.8v 0.2v, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. table 6f. ac characteristics, v dd = 2.5v 5%, v ddo = 1.8v 0.2v, t a = 0c to 70c note: electrical parameters are guaranteed ov er the specified ambient operating temper ature range, which is established when th e device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. all parameters measured at ? ? f max using a crystal input unless noted otherwise. terminated at 50 ? to v ddo /2. note 1: xtal_in can be overdriven by a single-ended lvcmos signal. please refer to application information section. note 2: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 3: this parameter is defined in accordance with jedec standard 65. note 4: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.18 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 48 52 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles symbol parameter test conditio ns minimum typical maximum units f max output frequency using external crystal 10 40 mhz using external clock source note 1 dc 100 mhz t sk(o) output skew; note 2, 3 80 ps tjit rms phase jitter (random) 25mhz, integration range: 100hz ? 1mhz 0.19 ps t r / t f output rise/fall time 20% to 80% 200 900 ps odc output duty cycle 47 53 % t en output enable time; note 4 enable1 4 cycles enable2 4 cycles t dis output disable time; note 4 enable1 4 cycles enable2 4 cycles
9 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet typical phase noise at 25mhz (2.5v core/2.5v output) raw phase noise data 25mhz rms phase jitter (random) 100hz to 1mhz = 0.26ps (typical) noise power(dbc/hz) offset frequency (hz)
10 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 1.8v core/1.8v lvcmos output load ac test circuit 3.3v core/1.8v lvcmos output load ac test circuit 2.5v core/2.5v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit 2.5v core/1.8v lvcmos output load ac test circuit scope qx gnd v dd, -1.65v5% 1.65v5% v ddo scope qx gnd v dd, -0.9v0.1v 0.9v0.1v v ddo scope qx gnd v dd -0.9v0.1v 2.4v0.9v v ddo 0.9v0.1v scope qx gnd v dd, -1.255% 1.25v5% v ddo scope qx gnd v dd -1.255% 2.05v5% v ddo 1.25v5% scope qx gnd v dd -0.9v0.1v 1.6v0.025% v ddo 0.9v0.1v
11 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet parameter measure ment information, continued output skew output rise/fall time output duty cycle/pulse width/period qx qy t sk(b) v ddo 2 v ddo 2 20% 80% 80% 20% t r t f bclk[0:5] bclk[0:5]
12 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet application information crystal input interface figure 2 shows an example of 83905 crystal interface with a parallel resonant crystal. the frequency accuracy can be fine tuned by adjusting the c1 and c2 values. for a parallel crystal with loading capacitance cl = 18pf, to start with, we suggest c1 = 15pf and c2 = 15pf. these values may be slightly fine tuned further to optimize the frequency accuracy for different board layouts. slightly increasing the c1 and c2 values will slightly reduce the frequency. slightly decreasing the c1 and c2 values will slightly increase the frequency. for the oscillator circuit below, r1 can be used, but is not required. for new designs, it is recommended that r1 not be used. figure 2. crystal input interface lvcmos to xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 3. the xtal_out pin can be left floating. the input edge rate can be as slow as 10ns. for lvcmos inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal in terference with the power rail and to reduce noise. this configurat ion requires that the output impedance of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the cr ystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 3. general diagram for lvcmos driver to xtal input interface xtal_in xtal_out c1 15p c2 15p x1 18pf parallel crystal r1 (optional) 0 xtal_in xtal_out ro rs zo = ro + rs 50 0.1f r1 r2 v dd v dd
13 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the t hermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis a nd/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of am kor?s thermally/electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) recommendations for unused input and output pins inputs: lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be le ft floating. there should be no trace attached. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
14 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet layout guideline figure 5 shows an example of 83905 application schematic. the schematic example focuses on functional connections and is not configuration specific. in this ex ample, the device is operated at v dd = 3.3v and v ddo = 1.8v. the crystal inputs are loaded with an 18pf load resonant quartz crystal. the tuning capacitors (c1, c2) are fairly accurate, but minor adjustments might be required. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set. for the lvcmos output drivers, two termination examples are shown in the schematic. for additional termination examples are shown in the lvcmos termination application note. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isol ation is required. the 83905 provides separate v dd and v ddo power supplies to isolate any high switching noise from coupling into the internal oscillator. in order to achieve the best possib le filtering, it is highly recommended that the 0.1uf capacitors on the device side of the ferrite beads be placed on the device side of the pcb as close to the power pins as possible. this is represented by the placement of these capacitors in the schematic . if space is limited, the ferrite beads, 10uf and 0.1uf capacitor co nnected to the board supplies can be placed on the opposite side of the pcb. if space permits, place all filter components on the device side of the board. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for a wide range of noise frequencies. this low-pass filter starts to attenuate noise at approximately 0khz. if a specific frequency noise component is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally, good general design practices for power plane voltage stability suggests adding bulk capacitance in the local area of all devices. figure 5. schematic of recommended layout
15 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet power considerations this section provides information on power di ssipation and junction temperature for the 83905. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 83905 is the sum of the core po wer plus the analog power plus the power dissipated due to t he load. the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd + i ddo ) = 3.465v *(10ma + 5ma) = 51.9mw ? output impedance r out power dissipation due to loading 50 ? to v dd /2 output current i out = v dd_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 7 ? )] = 30.4ma ? power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 7 ? * (30.4ma) 2 = 6.5mw per output ? total power dissipation on the r out total power (r out ) = 6.5mw * 6 = 39mw dynamic power dissipation at 25mhz power (25mhz) = c pd * frequency * (v dd ) 2 = 19pf * 25mhz * (3.465v) 2 = 5.70mw per output total power (25mhz) = 5.70mw * 6 = 34.2mw total power dissipation ? total power = power (core) max + total power (r out ) + total power (25mhz) = 51.98mw + 39mw + 34.2mw = 125.1mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature is 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction te mperature, the appropri ate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriat e value is 100.3c/w per table 7 below. therefore, tj for an ambient temperatur e of 70c with all outputs switching is: 70c + 0.125w *100.3c/w = 82.5c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary dep ending on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resistance ? ja for 16-lead tssop, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
16 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet reliability information table 8a. ? ja vs. air flow table for a 16-lead tssop table 8b. ? ja vs. air flow table for a 16-lead soic table 8c. ? ja vs. air flow table for a 20-lead vfqfn transistor count the transistor count for 83905: 339 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 78.8c/w 71.1c/w 66.2c/w ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 57.5c/w 50.3c/w 45.1c/w
17 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet package outline and package dimensions package outline - g suffix for 16-lead tssop table 9a. package dimensions for 16-lead tssop reference document: jedec publication 95, mo-153 package outline - m suffix for 16-lead soic table 9b. package dimensions for 16-lead soic reference document: jedec publication 95, ms-012 all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 ? 0 8 aaa 0.10 all dimensions in millimeters symbol minimum maximum n 16 a 1.35 1.75 a1 0.10 0.25 b 0.33 0.51 c 0.19 0.25 d 9.80 10.00 e 3.80 4.00 e 1.27 basic h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 8 150 il (n b d ) soic
18 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet package outline and package dimensions package outline - k suffix for 20-lead vfqfn table 10. package dimensions reference document: jedec publication 95, mo-220 note: the drawing and dimension data originate from idt package outline drawing psc-4170, rev03. 1. dimensions and tolerances conform to asme y14.5m-1994 2. all dimensions are in millimeters. all angles are in degrees. 3. n is the total number of terminals. 4. all specifications co mply with jedec mo-220. all dimensions in millimeters symbol minimum n ominal maximum n 20 a 0.80 1.00 a1 00.05 a3 0.2 ref. b 0.20 0.25 0.30 n d & n e 5 d & e 4.00 basic d2 & e2 1.95 2.25 e 0.50 basic l 0.45 0.55 0.65
19 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet ordering information table 11. ordering information part/order number marking package shipping packaging temperature 83905AMLF 83905aml ?lead-free? 16-lead soic tube 0 ? c to 70 ? c 83905AMLFt 83905aml ?lead-free? 16-lead soic tape & reel 0 ? c to 70 ? c 83905aglf 83905agl ?lead-free? 16-lead tssop tube 0 ? c to 70 ? c 83905aglft 83905agl ?lead-free? 16-lead tssop tape & reel 0 ? c to 70 ? c 83905aklf 3905al ?lead-free? 20-lead vfqfn tray 0 ? c to 70 ? c 83905aklft 3905al ?lead-free? 20-lead vfqfn tape & reel 0 ? c to 70 ? c
20 ?2016 integrated device technology, inc. revision d september 27, 2016 83905 datasheet revision history sheet rev table page description of change date a 2 added enable timing diagram. 3/28/05 bt6a - t6f 1 5 - 7 8 features section - added rms phase jitter bullet. ac characteristics tables - added rms phase jitter specs. added phase noise plot. 4/8/05 b t9 14 ordering information table - added tssop, non-lf part number. 4/25/05 b 11 12 added crystal input interfac e in application section. added schematic layout. 5/16/05 b 3 11 13 absolute maximum ratings - corrected 20-lead vfqfn package thermal impedance. added recommendations for unused input and output pins. corrected theta ja air flow table for 20-lead vfqfn. 10/2/06 b t9 11 12 17 added lvcmos to xtal interface section. added thermal release path section. ac characteristics table - added lead-free marking for 20-lead vfqfn package. 7/9/07 b t7b - t7c 3 12 14 16 absolute maximum ratings - updated tssop and vfqfn thermal impedance. updated thermal release path section. updated tssop and vfqfn thermal impedance. added note to vfqfn package outline. 1/24/08 b 15 added power considerations section. converted datasheet format. 7/20/09 b t10 19 removed leaded order-able parts from ordering information table 11/14/12 c t6d t9a t11 1, 15 1 7 14 17 18 19 deleted hiperclocks references. features, last bullet: updated packaging note. mixed ac characteristics tabl e - corrected typo, switched output rise/fall time spec with output duty cycle spec. replaced schematic. 16-lead tssop package table - corrected dimension a1 minimum = 0.05. updated vfqfn package outline page. ordering information table - deleted lead-fr ee note, and quantit y from tape and reel. 4/18/13 c 1 pin assignment: corrected 20-lead illustration cut-off text 2/27/14 c t6a - t6f t10 1 6 - 8 9 11 18 21 pin assignment, 20-lead vfqfn: removed the epad dimensions. changed note 1to xtal_in can be overdriv en by a single-ended lvcmos signal. please refer to application information section. deleted 3.3v phase noise plot deleted rms phase jitter graph. modified dimensions to reflect tightened tolerances. updated contact information. 8/6/14 d 2 figure 1 corrected. updated datasheet header/footer. deleted ?ics? prefix from part number throughout the datasheet 9/27/16
83905 datasheet 21 ?2016 integrated device technology, inc. revision d september 27, 2016 disclaimer integrated device technology, inc. (idt) reserves the right to modify the products an d/or specifications described h erein at any time, without notice, at id t's sole discretion. performance spec- ifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without represent ation or warranty of any ki nd, whether express or imp lied, including, but not lim ited to, the suitability of idt's product s for any particular purpose, an implied warranty of merchantability, or non-infringement of the inte llectual property rights of others. this docum ent is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involvi ng extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be rea- sonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other c ountries. other trademarks used herein are the property of idt or their respective third party owners. for datas heet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . integrated device technology, inc.. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com

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